RFCC-VLIW register file architecture for very long instruction word processors

The cost of register files increases explosively with increasing number of function units in VLIW(very long instruction word) processors.This paper describes a register file architecture.Where,the function units are grouped into several clusters and the register file is partitioned into several local register files.Each function unit cluster corresponds to a local register file and the function units can all directly access their register file.A global register file is used to connect all the clusters so function units in different clusters can exchange their operation results.Partitioning of the register file reduces the number of ports and then reduces the area,power and access time of register files.The global register file removes the data copy operation in clustered processors which improve the performance of clustered processors.Results show that it can reduce the performance losses to 13%.