A new DRAM cell technology using merged process with storage node and memory cell contact for 4 Gb DRAM and beyond

A new DRAM cell scheme using merged process with storage node and memory cell contact called BC is introduced for free alignment tolerance between memory cell contact and storage node. The new cell scheme and conventional COB stacked cell scheme are compared for the misalignment tolerance and photo and etch process issues. The new cell scheme is processed in 0.15 /spl mu/m minimum feature size and its results are described including vertical SEM pictures, capacitance-voltage data, and leakage current. This new cell scheme achieved the requirement of memory cell capacitance of 25 fF/cell in 0.30 /spl mu/m pitched 4 Gb DRAMs.