2004•Unpublished venueRequires access

Impact of metal gate work function on nano CMOS device performance

Yunfei Hou, Tony Low, Bin Xu, Mingfu Li, Ganesh Shankar Samudra, Dim‐Lee Kwong

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Abstract

We studied two effects in the metal gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for metal gate work function engineering are provided and technical challenges identified; (2) we presented a systematic study on gate tunneling characteristics of metal gate CMOSFETs. A reduction of gate to source/drain extension tunneling is found when using near mid-gap metal gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed.

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What this paper is about

We studied two effects in the metal gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for metal gate work function engineering are provided and technical challenges identified; (2) we presented a systematic study on gate tunneling characteristics of metal gate CMOSFETs. A reduction of gate to source/drain extension tunneling is found when using near mid-gap metal gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed.

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OpenAlex reports 8 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

We studied two effects in the metal gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for metal gate work function engineering are provided and technical challenges identified; (2) we presented a systematic study on gate tunneling characteristics of metal gate CMOSFETs. A reduction of gate to source/drain extension tunneling is found when using near mid-gap metal gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed.

Key concepts: Metal gate, CMOS, Gate dielectric, Materials science, Work function, Quantum tunnelling, Optoelectronics, MOSFET

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