1GHz monolithic high spectrum purity fractional-N frequency synthesizer with a 3-b third-order Delta-Sigma modulator
Baoyong Chi, Xiaolei Zhu, Shuilong Huang, Zhihua Wang
Abstract
Baoyong Chi, Xiaolei Zhu, Shuilong Huang, Zhihua Wang
Abstract
A 1GHz monolithic high spectrum purity fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator is implemented. A combined tuning technique of analog tuning and digital tuning is used to improve the phase noise of the frequency synthesizer. The power supply configuration is optimized to reduce the supply noise coupling, to improve the linearity of PFD and to increase the tuning range of the VCO. The on-chip VCO with a small gain utilizes the tail current source filtering technique to achieve a low phase noise, but it still keeps 100MHz tuning range due to the introduction of the on-chip digital controlled switched capacitor array. A pseudorandom sequence with a length of 2/sup 24/ is used for the 3-b third-order /spl Delta//spl Sigma/ modulator with LSB dithering resulting in less than 0.001ppm frequency resolution. The frequency synthesizer has been integrated on one chip in CMOS 0.18/spl mu/m process, the simulated results show the frequency synthesizer has a 14kHz loop bandwidth and a high spectrum purity, the maximum in-band phase noise is -106dBc/Hz, the phase noise is lower than -120dBc/Hz at 100kHz offset. And the frequency synthesizer has a fast settling time which is about 160/spl mu/s.
OpenAlex reports 6 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
A 1GHz monolithic high spectrum purity fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator is implemented. A combined tuning technique of analog tuning and digital tuning is used to improve the phase noise of the frequency synthesizer. The power supply configuration is optimized to reduce the supply noise coupling, to improve the linearity of PFD and to increase the tuning range of the VCO. The on-chip VCO with a small gain utilizes the tail current source filtering technique to achieve a low phase noise, but it still keeps 100MHz tuning range due to the introduction of the on-chip digital controlled switched capacitor array. A pseudorandom sequence with a length of 2/sup 24/ is used for the 3-b third-order /spl Delta//spl Sigma/ modulator with LSB dithering resulting in less than 0.001ppm frequency resolution. The frequency synthesizer has been integrated on one chip in CMOS 0.18/spl mu/m process, the simulated results show the frequency synthesizer has a 14kHz loop bandwidth and a high spectrum purity, the maximum in-band phase noise is -106dBc/Hz, the phase noise is lower than -120dBc/Hz at 100kHz offset. And the frequency synthesizer has a fast settling time which is about 160/spl mu/s.
Key concepts: Frequency synthesizer, Delta-sigma modulation, Phase noise, Direct digital synthesizer, Phase-locked loop, Voltage-controlled oscillator, Chip, Physics