Design of high performance and low power 16T full adder cell for sub-threshold technology

This paper presents a new structure of 1-bit full adder for sub-threshold technology. It compares full adder sub-circuits and also compares the proposed full adder with common full adders in terms of propagation delay, power consumption, power delay product and square power delay product in sub-threshold technology. HSPICE simulations show that the power dissipation, power delay product and square power delay product of the proposed 16T full adder is 7%, 19% and 25% better than the best common full adder TG, respectively. The full adder circuits are compared in 260 (mV) supply voltage.