Characterization of 6T CMOS SRAM in 90nm technology for various leakage reduction techniques

As the scale down the feature size of transistor, leakage power maximizes inversely. In present day's power dissipation is important factor .One of the major area where leakage is effective memory to reduce the leakage power in memory. In memory to reduce the leakage dissipation there are different types of technique were used in 6T Static RAM. The technique that can be implemented includes gated Vdd, Source basing, Sleep stack and MT-CMOS the technology used for 6T memory is 90nm using Tanner Tool_V13.0_LND.