A novel clock synchronizer for low-voltage clock distribution network

In this paper, we propose a fast clock synchronizer for the low-voltage clock distribution network to reduce the power consumption and to suppress the phase error. This proposed circuit will align the clock signals of the leaf nodes with the source of root in most 4 clock cycles and diminish the buffers of original clock driver chains. CTC and FTC are implemented to perform coarse and fine tuning separately in 2 and 3 clock cycles with one shared cycle and low-voltage phase detectors are also applied to meet the requirement of power supply. Interleaved delay units are introduced to improve the precision of coarse tuning and binary search scheme is employed to shorten the fine tuning periods. The proposed circuit is designed using TSMC 65 nm GP process with a least 0.6 V supply. Comparison with the H-tree clock network synthesized of single core of OpenSPARC T2 is applied in this paper. The experimental results show that the clock will get synchronized in most 4 cycles with the phase error suppressed under 48 ps and the power saving is up to 42%.