Implementation Methodology of High Performance Multi Byte Data Access Control of AMBA Bus
A. Anendhar, C Srilatha
Abstract
A. Anendhar, C Srilatha
Abstract
Abstract-- Earlier the memories used to have more speed than the processors. But with the invention of Microprocessors and Microcontroller the speed of the memory has become lesser than these processors. So with the improvement of Microprocessor these years, the memory access time has been a bottleneck which limits the system performance. Even though the system has high frequency every application needs to access the memory several times and the memories have lesser speed than the processor. So the memory accessing time definitely limits the system performance. This paper describes an approach to increase the system performance by using on-chip bus i.e. Advanced microcontroller Bus Architecture (AMBA) AHB bus with Burst operation, in the burst operation the data will be transferred from/to the sequential locations of the memory. Each transfer has definite time. This architecture may reduce the memory latencies and bandwidths. The result is that the memory accessing time will be reduced, which increases the system performance. Keywords-- ARM; AMBA; AHB; APB; Memory controller. I.
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Abstract-- Earlier the memories used to have more speed than the processors. But with the invention of Microprocessors and Microcontroller the speed of the memory has become lesser than these processors. So with the improvement of Microprocessor these years, the memory access time has been a bottleneck which limits the system performance. Even though the system has high frequency every application needs to access the memory several times and the memories have lesser speed than the processor. So the memory accessing time definitely limits the system performance. This paper describes an approach to increase the system performance by using on-chip bus i.e. Advanced microcontroller Bus Architecture (AMBA) AHB bus with Burst operation, in the burst operation the data will be transferred from/to the sequential locations of the memory. Each transfer has definite time. This architecture may reduce the memory latencies and bandwidths. The result is that the memory accessing time will be reduced, which increases the system performance. Keywords-- ARM; AMBA; AHB; APB; Memory controller. I.
Key concepts: Computer science, Interleaved memory, Uniform memory access, Embedded system, Registered memory, Physical address, Microprocessor, Computer hardware