Construct High-Speed SDRAM Memory Controller Using Multiple FIFO's for AHB Memory Slave Interface

The development of SOC design methodology has increased the ability to pack a lot of logic into a single chip and thus, has paved the way for compact devices, These devices integrate several components from different vendors and performing different functionality on a single chip. Bus based communication protocols have been proved very efficient for interconnecting these components. Advanced High performance bus (AHB) is a very popular communication protocol for SOCs. This protocol supports high speed communication and is thus, very apt for high speed communication between devices. Today's issue is the speed of fetching data from memories is unable to cope up with speed of processors since processors are getting faster day by day and memories getting bulky, hence fast memory controllers are needed that eventually increases memory efficiency. Memory controller is responsible to match speed of processor and memory one and the other side, so as to enable seamless communication. The challenge in interfacing SDRAM to AHB lies in the fact that the latency of SDRAM is not one cycle and thus, the idle times of AHB bus increase and thus, leading to under utilization of bus resources. In this project we develop a memory controller that aims at reducing the latency of SDRAM access by using local fifo to temporarily store the data to and from the SDRAM.