RTL design of reconfigurable multiplier

Multiplier is a fundamental unit of digital system and signal processing. A Booth multiplier using state machine has been designed and modeled for n bit multiplication. Functional verification of the design by RTL simulation for 8 bit, 16 bit, 32 bit and 128 bit using Model Sim has been shown. Synthesis has been performed for 16 bit, 32 bit and 128 bit using Xilinx. We have achieved 302.5 MHz as maximum operating frequency for 16 bit multiplication. The proposed Booth multiplier is efficient in terms of speed and area.