Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder

In this paper, a high performance 32/spl times/32-bit multiplier for a DSP core is proposed. The multiplier is composed of a novel sign select Booth encoder, an efficient data compressor block with a novel compound full-adder, and a 64-bit conditional sum adder with a separated carry generation block. The proposed 32/spl times/32-bit multiplier is designed by a full-custom method and there are about 28000 transistors in an active area of 1.59 mm/spl times/1.68 mm with 0.6 /spl mu/m CMOS technology. From the experimental results, the multiplication time of the 32/spl times/32-bit multiplier is about 9.8 ns at a 3.3 V power supply, and it consumes about 186 mW at 100 MHz.