2000•Journal of the Institute of Electronics Engineers of KoreaRequires access
Study on Chip Design & Implementation of 32 Bit Floating Point Compatible DSP
Jong-Sik Woo, Jin-Keun Seo, Jae‐Young Lim, Jusung Park
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Abstract
This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6 CMOS technology. The Chip has 450,000 gates complexity, area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.