Shi Gan
Abstract
A universal and efficient multi-DSP parallel processor based on FPGA is presented and tested with computer simulation. The simulation conclusion confirms that the Read-Write clock period accords with DSP's, so that the system can implement parallel process with high speed in and achieve the design goal.
A significance statement is not available in the OpenAlex record.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
A universal and efficient multi-DSP parallel processor based on FPGA is presented and tested with computer simulation. The simulation conclusion confirms that the Read-Write clock period accords with DSP's, so that the system can implement parallel process with high speed in and achieve the design goal.
Key concepts: Computer science, Digital signal processing, Field-programmable gate array, Process (computing), Embedded system, Digital signal processor, Texas Instruments DaVinci, Computer hardware