2009Journal of the Institute of Electronics Engineers of KoreaRequires access

A $4^{th}$-Order 1-bit Continuous-Time Sigma-Delta Modulator for Acoustic Sensor

Hyoung-Joong Kim, Min Woo Lee, Jeongjin Roh

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Abstract

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13- 1-Poly 8-metal CMOS technology, with a core area of . Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating from a 3.3-V supply.

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What this paper is about

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13- 1-Poly 8-metal CMOS technology, with a core area of . Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating from a 3.3-V supply.

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Available abstract

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13- 1-Poly 8-metal CMOS technology, with a core area of . Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating from a 3.3-V supply.

Key concepts: Delta-sigma modulation, Oversampling, Feed forward, CMOS, Bandwidth (computing), Quantization (signal processing), Electronic engineering, Linearity

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