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An Improved Pipelined ADC Architecture

Cheng Chen

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Abstract

Based on analysis of the traditional 1.5-bit/stage pipelined ADC an improved architecture is presented.The non-monotonicity of the traditional architecture caused at the last stage is eliminated.Simulation results show that for the improved 10-bit pipelined ADC maximum 0.83-bit ENOB over the traditional one can be achieved without much increase in power dissipation and area as it is implemented.

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What this paper is about

Based on analysis of the traditional 1.5-bit/stage pipelined ADC an improved architecture is presented.The non-monotonicity of the traditional architecture caused at the last stage is eliminated.Simulation results show that for the improved 10-bit pipelined ADC maximum 0.83-bit ENOB over the traditional one can be achieved without much increase in power dissipation and area as it is implemented.

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Available abstract

Based on analysis of the traditional 1.5-bit/stage pipelined ADC an improved architecture is presented.The non-monotonicity of the traditional architecture caused at the last stage is eliminated.Simulation results show that for the improved 10-bit pipelined ADC maximum 0.83-bit ENOB over the traditional one can be achieved without much increase in power dissipation and area as it is implemented.

Key concepts: Effective number of bits, Computer science, Dissipation, Architecture, Power (physics), Stage (stratigraphy), Power consumption, CMOS

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