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2018•IOP Conference Series Materials Science and EngineeringOpen access

Research of Design Technologies for 8-bit High Speed Low Power Pipelined ADC

JU Shui-rong, Yahua Meng, Zhen Wang, Huan Li

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Abstract

8-bit, 80MS/s low power ADC is presented in this paper by using seven stage Pipelined architecture. To reduce the chip size and power of total ADC, and improve the harmonic distortion and noise property, MDAC in first sub-ADC is considered focused, The whole ADC was designed in 0.18μm CMOS process, the SNR of the ADC is 53dB, ENOB is 7.98bits. The total chip size is only 0.56mm2, as well as the typical power current is only 22mA. The Performance requirement of the ADC is achieved.

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What this paper is about

8-bit, 80MS/s low power ADC is presented in this paper by using seven stage Pipelined architecture. To reduce the chip size and power of total ADC, and improve the harmonic distortion and noise property, MDAC in first sub-ADC is considered focused, The whole ADC was designed in 0.18μm CMOS process, the SNR of the ADC is 53dB, ENOB is 7.98bits. The total chip size is only 0.56mm2, as well as the typical power current is only 22mA. The Performance requirement of the ADC is achieved.

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Available abstract

8-bit, 80MS/s low power ADC is presented in this paper by using seven stage Pipelined architecture. To reduce the chip size and power of total ADC, and improve the harmonic distortion and noise property, MDAC in first sub-ADC is considered focused, The whole ADC was designed in 0.18μm CMOS process, the SNR of the ADC is 53dB, ENOB is 7.98bits. The total chip size is only 0.56mm2, as well as the typical power current is only 22mA. The Performance requirement of the ADC is achieved.

Key concepts: Effective number of bits, CMOS, Chip, Power (physics), Total harmonic distortion, Computer science, Successive approximation ADC, Power consumption

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