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A Fully Differential Operational Amplifier for Pipelined ADC

Guo Xiao-l

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Abstract

Based on CMOS 0. 18um process,a two- stage Fully Differential Operational Amplifier used in Pipelined ADC was put forward. The operational amplifier( opamp) was composed of telescopic cascade input stage and a common- source output gain stage. A Miller compensation circuit and clock feed through frequency compensation( CFFC) circuit were used for the sake of phase margin and settling time. Above all,a steady common mode feedback( CMFB) circuit was adopted. Simulation results show that,under 1.8V supply power with 2 pF capacitive load,the proposed opamp has a 81. 09 dB DC gain,a 792. 1MHz unity gain bandwidth,a 47. 98° phase margin,and a39. 12ns settling time. The opamp has high gain,sufficient phase margin and low settling time which is applicable for stage gain circuit and sample and hold circuit of high resolution pipelined ADC.

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What this paper is about

Based on CMOS 0. 18um process,a two- stage Fully Differential Operational Amplifier used in Pipelined ADC was put forward. The operational amplifier( opamp) was composed of telescopic cascade input stage and a common- source output gain stage. A Miller compensation circuit and clock feed through frequency compensation( CFFC) circuit were used for the sake of phase margin and settling time. Above all,a steady common mode feedback( CMFB) circuit was adopted. Simulation results show that,under 1.8V supply power with 2 pF capacitive load,the proposed opamp has a 81. 09 dB DC gain,a 792. 1MHz unity gain bandwidth,a 47. 98° phase margin,and a39. 12ns settling time. The opamp has high gain,sufficient phase margin and low settling time which is applicable for stage gain circuit and sample and hold circuit of high resolution pipelined ADC.

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Available abstract

Based on CMOS 0. 18um process,a two- stage Fully Differential Operational Amplifier used in Pipelined ADC was put forward. The operational amplifier( opamp) was composed of telescopic cascade input stage and a common- source output gain stage. A Miller compensation circuit and clock feed through frequency compensation( CFFC) circuit were used for the sake of phase margin and settling time. Above all,a steady common mode feedback( CMFB) circuit was adopted. Simulation results show that,under 1.8V supply power with 2 pF capacitive load,the proposed opamp has a 81. 09 dB DC gain,a 792. 1MHz unity gain bandwidth,a 47. 98° phase margin,and a39. 12ns settling time. The opamp has high gain,sufficient phase margin and low settling time which is applicable for stage gain circuit and sample and hold circuit of high resolution pipelined ADC.

Key concepts: Phase margin, Operational amplifier, Fully differential amplifier, Open-loop gain, Gain–bandwidth product, Frequency compensation, Current-feedback operational amplifier, Electronic engineering

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