Design of a frame synchronization circuit based on FPGA
Hu Le
Abstract
Hu Le
Abstract
The principle of a frame synchronization in digital communiction based on FPGA is described.Then using MAX+PLUSII,digital communication frame synchronization circuit is designed through VHDL language and graphic editor.The design of key part is elaborated,Top file and correlative simulation figure are presented,The circuit is integreted in chip of FPGA.It is the base of digitization and integration in communication(system.)
OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
The principle of a frame synchronization in digital communiction based on FPGA is described.Then using MAX+PLUSII,digital communication frame synchronization circuit is designed through VHDL language and graphic editor.The design of key part is elaborated,Top file and correlative simulation figure are presented,The circuit is integreted in chip of FPGA.It is the base of digitization and integration in communication(system.)
Key concepts: VHDL, Field-programmable gate array, Computer science, Synchronization (alternating current), Frame (networking), Frame synchronization, Digitization, Computer hardware