Application of hardware description language VHDL in the digital system design

VHDL,as a new type of hardware description language, is used to describe,simulate and automatically design digital system.Nowadays,it becomes a key technology in electronic design automatic(EDA).The method and process using VHDL to design digital system is presented through an example of multiplier design.The anticipative target is achieved through simulation.The result shows that VHDL is strong in hardware description and flexible in design method.It could reduce the design difficulty of digital system and improve efficiency.