2014MicroprocessorsRequires access

Gigabit Ethernet's Design and Implementation Based on SerDes

Baisong Pan

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Abstract

The backplane's interconnection is achieved by using SerDes as the PHYsical layer so that each unit isplugged into the backplane board interconnects by Gigabit Ethernet protocol. This paper describes the basic architecture and interconnection method. The interface of Gigabit Ethernet is realized by using the chip of cycloneIV from Altera and is interconnected with Broadcom's Gigabit Ethernet switch chip via SerDes. The test results and conclusions of the design are completely given in the paper.

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What this paper is about

The backplane's interconnection is achieved by using SerDes as the PHYsical layer so that each unit isplugged into the backplane board interconnects by Gigabit Ethernet protocol. This paper describes the basic architecture and interconnection method. The interface of Gigabit Ethernet is realized by using the chip of cycloneIV from Altera and is interconnected with Broadcom's Gigabit Ethernet switch chip via SerDes. The test results and conclusions of the design are completely given in the paper.

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Available abstract

The backplane's interconnection is achieved by using SerDes as the PHYsical layer so that each unit isplugged into the backplane board interconnects by Gigabit Ethernet protocol. This paper describes the basic architecture and interconnection method. The interface of Gigabit Ethernet is realized by using the chip of cycloneIV from Altera and is interconnected with Broadcom's Gigabit Ethernet switch chip via SerDes. The test results and conclusions of the design are completely given in the paper.

Key concepts: SerDes, Gigabit Ethernet, Backplane, Computer science, Carrier Ethernet, Ethernet Powerlink, Gigabit, Embedded system

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