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A Low Phase Noise ΔΣ Fractional-N Frequency Synthesizer for UHF RFID Reader

Zongsheng Lai

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Abstract

A low phase noise fractional-N frequency synthesizer for CMOS UHF RFID reader is introduced in this paper. The phase noise requirements are summarized for the EPC global C1G2 and ETSI multi-protocol operation. A low drop-output regulator is presented to improve the phase noise performance of the VCO. Based on the error-feedback delta-sigma modulator,a coefficient reconfiguring technology has been introduced to improve the phase noise performance at intermediate frequency band. The proposed circuit is implemented with 0.18 μm RF CMOS process. The fractional-N frequency synthesizer achieves a phase noise of-108 dBc/Hz and-129.8 dBc/Hz at 200 kHz and 1 MHz offset from the carrier respectively. The whole chip draws 9.6 mA from the multiple power supply configuration.

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What this paper is about

A low phase noise fractional-N frequency synthesizer for CMOS UHF RFID reader is introduced in this paper. The phase noise requirements are summarized for the EPC global C1G2 and ETSI multi-protocol operation. A low drop-output regulator is presented to improve the phase noise performance of the VCO. Based on the error-feedback delta-sigma modulator,a coefficient reconfiguring technology has been introduced to improve the phase noise performance at intermediate frequency band. The proposed circuit is implemented with 0.18 μm RF CMOS process. The fractional-N frequency synthesizer achieves a phase noise of-108 dBc/Hz and-129.8 dBc/Hz at 200 kHz and 1 MHz offset from the carrier respectively. The whole chip draws 9.6 mA from the multiple power supply configuration.

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Available abstract

A low phase noise fractional-N frequency synthesizer for CMOS UHF RFID reader is introduced in this paper. The phase noise requirements are summarized for the EPC global C1G2 and ETSI multi-protocol operation. A low drop-output regulator is presented to improve the phase noise performance of the VCO. Based on the error-feedback delta-sigma modulator,a coefficient reconfiguring technology has been introduced to improve the phase noise performance at intermediate frequency band. The proposed circuit is implemented with 0.18 μm RF CMOS process. The fractional-N frequency synthesizer achieves a phase noise of-108 dBc/Hz and-129.8 dBc/Hz at 200 kHz and 1 MHz offset from the carrier respectively. The whole chip draws 9.6 mA from the multiple power supply configuration.

Key concepts: Phase noise, dBc, Frequency synthesizer, Ultra high frequency, CMOS, Electrical engineering, Voltage-controlled oscillator, Offset (computer science)

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