2013Electrical Measurement & InstrumentationRequires access

The FPGA Implementation of Digital Down Conversion Based on the CORDIC Algorithm

YU Yan-feng

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Abstract

The FPGA implementation of digital down convert based on the CORDIC algorithm is introduced.The method can also complete the NCO function and mixer function.The shortcoming such as occupying FPGA multiplier and a lot of resources of ROM,outputting spectrum spurious larger,can be overcoming.The article describes the principles of the CORDIC algorithm,and discusses the digital down-conversion architecture principle based on the CORDIC algorithm and the specific methods of the FPGA implementation.The method simulates filter and system for function and timing in the Quartus II and Modelsim platform.The test shows that the program correctly,and effectively save the FPGA hardware resources.

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What this paper is about

The FPGA implementation of digital down convert based on the CORDIC algorithm is introduced.The method can also complete the NCO function and mixer function.The shortcoming such as occupying FPGA multiplier and a lot of resources of ROM,outputting spectrum spurious larger,can be overcoming.The article describes the principles of the CORDIC algorithm,and discusses the digital down-conversion architecture principle based on the CORDIC algorithm and the specific methods of the FPGA implementation.The method simulates filter and system for function and timing in the Quartus II and Modelsim platform.The test shows that the program correctly,and effectively save the FPGA hardware resources.

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Available abstract

The FPGA implementation of digital down convert based on the CORDIC algorithm is introduced.The method can also complete the NCO function and mixer function.The shortcoming such as occupying FPGA multiplier and a lot of resources of ROM,outputting spectrum spurious larger,can be overcoming.The article describes the principles of the CORDIC algorithm,and discusses the digital down-conversion architecture principle based on the CORDIC algorithm and the specific methods of the FPGA implementation.The method simulates filter and system for function and timing in the Quartus II and Modelsim platform.The test shows that the program correctly,and effectively save the FPGA hardware resources.

Key concepts: CORDIC, ModelSim, Field-programmable gate array, Computer science, Multiplier (economics), Computer hardware, Digital filter, Spurious relationship

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