Research of FIR digital filter implementation with FPGA

In order to research different implementations of FIR digital filter with FPGA on their resource consuming as well as the speed performance,the improved serial structure,parallel structure and DA structure of FIR digital filter were respectively implemented with Verilog HDL on the Xilinx ISE10.1 development platform,and then simulated on the Modelsim sim-ulation platform.It turns out that the implementation of improved serial structure consumes resource least but the filter speed is low,and the parallel structure has a fastest filter speed but consumes resources most.Whereas,the filter speed of DA structure only depends on the width of input data,so its filter speed is usually faster than improved serial structure but the consuming resource is less then parallel structure.