2010•MicroprocessorsRequires access

A Novel Method for the Online Debug of Embedded Processors

Huang Yang-bo

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Abstract

Aimed at enabling the online debug for embedded processors that does not have debug interface,a novel method is proposed by introducing a versatile debug module.This debug module constructed a breakpoint mechanism by introducing a dedicated debug interrupt and the corresponding debug routine;Set breakpoints at many code lines is enabled by a novel address mapping scheme based on a dual port RAM.It is shown from engineering practice that with the ability of debugging smart embedded processors gained by this new debug method,the developing efficiency was obviously improved.

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What this paper is about

Aimed at enabling the online debug for embedded processors that does not have debug interface,a novel method is proposed by introducing a versatile debug module.This debug module constructed a breakpoint mechanism by introducing a dedicated debug interrupt and the corresponding debug routine;Set breakpoints at many code lines is enabled by a novel address mapping scheme based on a dual port RAM.It is shown from engineering practice that with the ability of debugging smart embedded processors gained by this new debug method,the developing efficiency was obviously improved.

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Available abstract

Aimed at enabling the online debug for embedded processors that does not have debug interface,a novel method is proposed by introducing a versatile debug module.This debug module constructed a breakpoint mechanism by introducing a dedicated debug interrupt and the corresponding debug routine;Set breakpoints at many code lines is enabled by a novel address mapping scheme based on a dual port RAM.It is shown from engineering practice that with the ability of debugging smart embedded processors gained by this new debug method,the developing efficiency was obviously improved.

Key concepts: Debugging, Background debug mode interface, Computer science, Embedded system, Interface (matter), Set (abstract data type), Interrupt, Scheme (mathematics)

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