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VLSI Architecture of a High Performance FFT Processor

Yu Feng

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Abstract

The VLSI architecture of a high performance FFT processor is described in the paper A particularly simple way to control radix4 FFT hardware is developed The method produces the indices both for inputs of each butterfly operation and for the appropriate twiddle factors The memory assignment is inplace to minimize memory size,and memorybank conflictfree to allow simultaneous access to the four data needed for calculation of each of the radix4 butterflies,hence the processor can access all the operands concurrently in one cycle Using Verilog HDL,a 1024point FFT processor is designed,which can process frames of 16bit complex samples at one output sample per 100 MHz clock cycle,thus performing a 1024point transform in 128 μs

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What this paper is about

The VLSI architecture of a high performance FFT processor is described in the paper A particularly simple way to control radix4 FFT hardware is developed The method produces the indices both for inputs of each butterfly operation and for the appropriate twiddle factors The memory assignment is inplace to minimize memory size,and memorybank conflictfree to allow simultaneous access to the four data needed for calculation of each of the radix4 butterflies,hence the processor can access all the operands concurrently in one cycle Using Verilog HDL,a 1024point FFT processor is designed,which can process frames of 16bit complex samples at one output sample per 100 MHz clock cycle,thus performing a 1024point transform in 128 μs

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Available abstract

The VLSI architecture of a high performance FFT processor is described in the paper A particularly simple way to control radix4 FFT hardware is developed The method produces the indices both for inputs of each butterfly operation and for the appropriate twiddle factors The memory assignment is inplace to minimize memory size,and memorybank conflictfree to allow simultaneous access to the four data needed for calculation of each of the radix4 butterflies,hence the processor can access all the operands concurrently in one cycle Using Verilog HDL,a 1024point FFT processor is designed,which can process frames of 16bit complex samples at one output sample per 100 MHz clock cycle,thus performing a 1024point transform in 128 μs

Key concepts: Fast Fourier transform, Very-large-scale integration, Computer science, Verilog, Parallel computing, Twiddle factor, Operand, Computer hardware

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