Design and Implementation of High Throughput FFT Processor

A parallel architecture for the implementation of the radix 4 and mixed radix FFT algorithm is presented The dedicated parallel memory mapping algorithm with the feature of minimal memory size relies on the in place calculation property of the FFT algorithm, and can simultaneously access to all the data needed for calculation of each butterfly The address generation of twiddle factors only need simple operation in this algorithm The hardware complexity of the butterfly processor is reduced by using 3 real multipliers algorithm for a complex multiplier The processor can be configured for transforms of lengths N , where N is power of two The implementation is on an Altera chip EP200K400E using Altera Quartus II 2 0 Operating at 89MHz clock frequency the processor computes a complex 1024 point FFT within 14 1μs and 4096 point FFT within 67μs