2005Unpublished venueRequires access

Design of Finite State Machine Based on VHDL

Chen Wen-kai

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Abstract

Comparing two finite state machine, declare how to use VHDL to design a reliable and stable finite state machine. Due to the difference between the two finite state machine, then their stability is different with new method proposed in this paper, we can design a reliable and stable finite state machine when take normal code method.

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What this paper is about

Comparing two finite state machine, declare how to use VHDL to design a reliable and stable finite state machine. Due to the difference between the two finite state machine, then their stability is different with new method proposed in this paper, we can design a reliable and stable finite state machine when take normal code method.

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Available abstract

Comparing two finite state machine, declare how to use VHDL to design a reliable and stable finite state machine. Due to the difference between the two finite state machine, then their stability is different with new method proposed in this paper, we can design a reliable and stable finite state machine when take normal code method.

Key concepts: Finite-state machine, VHDL, State (computer science), Computer science, Virtual finite-state machine, Finite state, Extended finite-state machine, Code (set theory)

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