2012•Advanced materials researchOpen access

Design of Finite State Machine Based on VHDL

Zhi Ping Zhu, Yong Qin Liu, Hong Sheng, Feng Ye

Abstract

Different encoding scheme and method for process description of state machine are analyzed in detail, and the advantages and disadvantages of each are pointed out. The general state machine design method is given by a specific example program, according to the actual need, designers can choose different encoding scheme and method for process description to design.

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Key concepts: Finite-state machine, Scheme (mathematics), VHDL, State (computer science), Encoding (memory), Process (computing), Computer science, Abstract state machines