Design and Implementation of SEU Hard Core Detection Circuit

Current Field Programmable Gate Array(FPGA) chip can only be erased and configured periodically and repeatedly during the Single Event Upset(SEU) error detection,and this is not a continuous error detection and correction method.Aiming at this problem,this paper presents a continuous SEU hard core detection circuit with real-time error detection information output for external circuits.The circuit improves the traditional FPGA frame storage structureca and can work continuously for read-back Cyclic Redundancy Check(CRC) without affecting the normal state of FPGA.The design has been used in FDP3P7 FPGA chip which is designed independently.Test results indicate that the SEU hard core detection circuit can work continuously on the configuration bit-stream read-back CRC in the 50 MHz frequency and real-time error detection information output correctly.