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The FPGA Design and Development of the Under Levels Computer in Asynchronous Serial Communication

Meng Fan-zhi

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Abstract

This paper presents how to use the FPGA to design the under levels computer in asynchronous serial communication,and focuses on the key design points of the receiving module in FPGA,together with the simulated timing graphs;This paper also provides a type of frame communication protocol and the processing flow of the soft microcontroller core PicoBlaze to translate the protocol.The asynchronous serial communication module designed in this paper is running stably and reliably in the real system,which proves the correctness of this paper.

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What this paper is about

This paper presents how to use the FPGA to design the under levels computer in asynchronous serial communication,and focuses on the key design points of the receiving module in FPGA,together with the simulated timing graphs;This paper also provides a type of frame communication protocol and the processing flow of the soft microcontroller core PicoBlaze to translate the protocol.The asynchronous serial communication module designed in this paper is running stably and reliably in the real system,which proves the correctness of this paper.

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Available abstract

This paper presents how to use the FPGA to design the under levels computer in asynchronous serial communication,and focuses on the key design points of the receiving module in FPGA,together with the simulated timing graphs;This paper also provides a type of frame communication protocol and the processing flow of the soft microcontroller core PicoBlaze to translate the protocol.The asynchronous serial communication module designed in this paper is running stably and reliably in the real system,which proves the correctness of this paper.

Key concepts: Computer science, Asynchronous communication, Field-programmable gate array, Serial communication, Correctness, Frame (networking), Synchronous serial communication, Microcontroller

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