2011Journal of Xuchang UniversityRequires access

Design of High-speed Image Processing Embedded System based on FPGA and DSP

Lihui Guo

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Abstract

A high-speed image processing embedded system based on the field programmable gate array and high-speed digital signal processor is designed in this paper.A novel data transmission structure with a dual-port RAM which is divided into two halves is applied to buff the high-speed real-time image data by means of Ping-pong technique.Because all work in the system is divided between the FPGA and DSP in the form of the pipelined,it is 25% higher than the processing system based on the single DSP in performance.This system is easy to transplant other algorithms for its reconfigurability.

About this research paper

What this paper is about

A high-speed image processing embedded system based on the field programmable gate array and high-speed digital signal processor is designed in this paper.A novel data transmission structure with a dual-port RAM which is divided into two halves is applied to buff the high-speed real-time image data by means of Ping-pong technique.Because all work in the system is divided between the FPGA and DSP in the form of the pipelined,it is 25% higher than the processing system based on the single DSP in performance.This system is easy to transplant other algorithms for its reconfigurability.

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Available abstract

A high-speed image processing embedded system based on the field programmable gate array and high-speed digital signal processor is designed in this paper.A novel data transmission structure with a dual-port RAM which is divided into two halves is applied to buff the high-speed real-time image data by means of Ping-pong technique.Because all work in the system is divided between the FPGA and DSP in the form of the pipelined,it is 25% higher than the processing system based on the single DSP in performance.This system is easy to transplant other algorithms for its reconfigurability.

Key concepts: Digital signal processing, Reconfigurability, Field-programmable gate array, Computer science, Computer hardware, Embedded system, Image processing, Digital signal processor

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