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Design of RISC Coprocessor

Xiaoyang Zeng

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Abstract

Aiming at the slow operating speed of existing AES and SHA-3 candidates Gr stl algorithm,this paper presents a design scheme for algorithm acceleration using Reduced Instruction Set Computer(RISC) coprocessor.Data cache is multiplexed as look-up table by the coprocessor for acceleration.Several specific instructions are added to the RISC instruction set architecture to accelerate the operation.Experimental results show that the scheme can reduce hardware cost compared with the implementation using traditional parallel on-chip look-up.

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What this paper is about

Aiming at the slow operating speed of existing AES and SHA-3 candidates Gr stl algorithm,this paper presents a design scheme for algorithm acceleration using Reduced Instruction Set Computer(RISC) coprocessor.Data cache is multiplexed as look-up table by the coprocessor for acceleration.Several specific instructions are added to the RISC instruction set architecture to accelerate the operation.Experimental results show that the scheme can reduce hardware cost compared with the implementation using traditional parallel on-chip look-up.

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Available abstract

Aiming at the slow operating speed of existing AES and SHA-3 candidates Gr stl algorithm,this paper presents a design scheme for algorithm acceleration using Reduced Instruction Set Computer(RISC) coprocessor.Data cache is multiplexed as look-up table by the coprocessor for acceleration.Several specific instructions are added to the RISC instruction set architecture to accelerate the operation.Experimental results show that the scheme can reduce hardware cost compared with the implementation using traditional parallel on-chip look-up.

Key concepts: Coprocessor, Computer science, Reduced instruction set computing, Instruction set, Cache, Acceleration, Scheme (mathematics), Embedded system

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