Design of 3DES Arithmetic Encryption for SRAM Technique FPGA
LU Guo-bin
Abstract
LU Guo-bin
Abstract
3DES arithmetic encryption method for SRAM technique FPGA is introduced in this paper.It describes the model of the 3DES arithmetic encryption and the process of 3DES hardware design in detail.Finally,the 3DES arithmetic encrypt simulation timing diagram and the result of implementation on FPGA are presented in the paper.
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3DES arithmetic encryption method for SRAM technique FPGA is introduced in this paper.It describes the model of the 3DES arithmetic encryption and the process of 3DES hardware design in detail.Finally,the 3DES arithmetic encrypt simulation timing diagram and the result of implementation on FPGA are presented in the paper.
Key concepts: Encryption, Field-programmable gate array, Embedded system, Computer science, Static random-access memory, Arithmetic, Computer hardware, Operating system