Research on a parallel adder with 4 binary addends and its interface

The arithmetic logic unit(ALU) decides the performance of the Central Processing Unit(CPU),while the adder decides that of the ALU.To improve the performance of the CPU,a parallel adder with 4 binary addends and its interface are proposed.The working principle and process of the novel adder are discussed,and its interface extension is described.Finally,the MAX+PLUS Ⅱ is adopted to simulate and validate the proposed adder.Experimental results indicate that the proposed design scheme is not only reasonable,but it can also calculate 4 binary addends faster than a carry look-ahead adder using the serial adding scheme.