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2006•Telecommunication EngineeringRequires access

FPGA Implementation of a High-Speed Viterbi Decoder

Hua Wang

Open publisher page 1 citations

Abstract

The FPGA implementation of a high-speed Viterbi decoder is presented.In order to improve the speed of the decoder,an all-parallel structure of the add-compare-select unit and the register exchange algorithm are adopted.The hardware resources are reduced by means of the majority rule and some optimizations.The maximal data output speed of this decoder is up to 90Mbps.Simulation and FPGA implementation show that this design is feasible.

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What this paper is about

The FPGA implementation of a high-speed Viterbi decoder is presented.In order to improve the speed of the decoder,an all-parallel structure of the add-compare-select unit and the register exchange algorithm are adopted.The hardware resources are reduced by means of the majority rule and some optimizations.The maximal data output speed of this decoder is up to 90Mbps.Simulation and FPGA implementation show that this design is feasible.

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Available abstract

The FPGA implementation of a high-speed Viterbi decoder is presented.In order to improve the speed of the decoder,an all-parallel structure of the add-compare-select unit and the register exchange algorithm are adopted.The hardware resources are reduced by means of the majority rule and some optimizations.The maximal data output speed of this decoder is up to 90Mbps.Simulation and FPGA implementation show that this design is feasible.

Key concepts: Viterbi decoder, Soft-decision decoder, Field-programmable gate array, Computer science, Soft output Viterbi algorithm, Viterbi algorithm, Computer hardware, Speedup

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