Implemented architecture design of deblocking filter for H.264

An implemented architecture of deblocking filter was proposed to improve the performance of deblocking filter in H.264.With a novel filtering order, only 252 cycles were needed to perform the deblocking filter of a macroblock,consequently the unfiltered data storage was reduced to a 4×4 block instead of a whole 16×16 macroblock.According to the data reuse strategy,the intermediate data storage was also reduced from a whole 16×16 macroblock to four 4×4 blocks.With an optimized pipeline design,the data access to bus was reduced efficiently.The resulting design could achieve 100 MHz with only gate counts of 14.2×103 by using 0.18 μm technology.Compared with former designs,the proposed deblocking filter architecture can achieve better performance with smaller hardware area.At 100 MHz,the proposed design can perform real-time deblocking filter for high definition video application of H.264.