Algorithm and circuit design for H.264 deblocking filter

The deblocking filter in the H.264 video coding standard can improve video quality but with huge computational complexity.A high performance,small area deblocking filter was designed based on a deblocking algorithm,which executes read/write operations on external memory with filtering computations in parallel based on an advanced filtering order.The circuit was implemented in 0.18 μm process by Verilog.The results show that it can achieve 111.7 frame/s for 1 280×720 resolution video at 140 MHz with an area of no more than 16.5×103 gates.The design has 32.5% less area and 79.3% better performance than other deblocking filters.