Hao Zhu
Abstract
To study method to implement 16 order FIR filter based on FPGA, FIR filter is described with VHDL language and the mode of skeleton diagram. And it is simulated experementally and timing analysis proceeds in MAX+plus II.With the design, how to accelerate the operation and optimize the availability of hardware resource are discussed.
OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
To study method to implement 16 order FIR filter based on FPGA, FIR filter is described with VHDL language and the mode of skeleton diagram. And it is simulated experementally and timing analysis proceeds in MAX+plus II.With the design, how to accelerate the operation and optimize the availability of hardware resource are discussed.
Key concepts: VHDL, Field-programmable gate array, Finite impulse response, Filter (signal processing), Computer science, Diagram, Filter design, Computer hardware