2011•Journal of Military Communications TechnologyRequires access

Design and Implementation of Reduced Hardware Protocol Stack Based on FPGA

XU Guang-jie

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Abstract

Accuracy and high speed are always the basic standard in data transmission.Aiming at the application of massive data transmission through high speed network,hardware behavior description language was used to transplant the reduced communication protocol stack into FPGA platform in the framework of TCP/IP.Thus the data can be transmited by UDP protocol to suit the demand of massive throughput of data.It was made possible to reach the performance of gigabit ethernet standard in the promise of accuracy.Attempt was made to get the reduced hardware protocol stack into block in this work.So it is convenient to be embeded into the devices or the ICs which need data transmission through gigabit ethernet net.

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What this paper is about

Accuracy and high speed are always the basic standard in data transmission.Aiming at the application of massive data transmission through high speed network,hardware behavior description language was used to transplant the reduced communication protocol stack into FPGA platform in the framework of TCP/IP.Thus the data can be transmited by UDP protocol to suit the demand of massive throughput of data.It was made possible to reach the performance of gigabit ethernet standard in the promise of accuracy.Attempt was made to get the reduced hardware protocol stack into block in this work.So it is convenient to be embeded into the devices or the ICs which need data transmission through gigabit ethernet net.

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Available abstract

Accuracy and high speed are always the basic standard in data transmission.Aiming at the application of massive data transmission through high speed network,hardware behavior description language was used to transplant the reduced communication protocol stack into FPGA platform in the framework of TCP/IP.Thus the data can be transmited by UDP protocol to suit the demand of massive throughput of data.It was made possible to reach the performance of gigabit ethernet standard in the promise of accuracy.Attempt was made to get the reduced hardware protocol stack into block in this work.So it is convenient to be embeded into the devices or the ICs which need data transmission through gigabit ethernet net.

Key concepts: Computer science, Gigabit Ethernet, Protocol stack, Field-programmable gate array, Ethernet, Embedded system, ATA over Ethernet, Network interface controller

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