FPGA-based parallel DDS

A method of the parallel processing techniques was introduced to increase the direct digital synthesizer(DDS)system clock frequency.The realization methods and the experimental results of a fried programmable gate array(FPGA)-based DDS circuit with a system clock frequency of 400MHz were given.In this circuit,the direct intermediate output method was used,the output signal frequency range,frequency resolution and spurious suppression were 250MHz～350MHz,6Hz and 50dB respectively.This DDS circuit have the advantage of simple to interface,flexible to use and can be used in wide bandwidth signal production in the field of radar and electronic warfare.