Design of High Speed and High Gain CMOS Operational Amplifier

A high-speed and high-gain operational amplifier used in S/H circuit is designed.The operational amplifier is based on the structure of the full-differential gain-boosting folded cascade.The frequency compensation capacitors appended in the input signal way eliminates the effect of the zero-pole doublet on the settling-time of op amp.The phase margin is improved by optimizing the non-dominant pole of the main op amp.Simulations with 0.35 μm CMOS process model showed that the operational amplifier has a DC open gain of 106 dB,an unity-gain bandwidth of 821 MHz(Load capacitor 8 pF)with 61°phase margin and a slew rate of 586 V/μs,and meets the performance requirements of the S/H circuit for 12 bit 50 MS/s pipeline ADC.