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2020•Unpublished venueRequires access

High Performance Operational Amplifier with 90dB Gain in SCL 180nm Technology

Surya Padma, Sounak Das, Subhajit Sen, C.D. Parikh

Open publisher page 12 citations

Abstract

This paper presents the design and implementation of a high-speed, high-gain fully differential opamp. The architecture consists of a telescopic cascode differential amplifier followed by a modified common-source second stage that includes an intermediate push-pull stage, individual CMFB circuits including frequency compensation for the first and second stages, RC Miller compensation for the main op-amp, and dc bias circuit blocks. The circuit is implemented in SCL 180nm technology, including layout and post-layout extracted characterization. It achieves a DC gain of 90dB with phase margin of 58° at 530MHz for a load of 1pF. Output voltage swing is +/-600mV for a +/-900mV supply. A sample-and-hold circuit built with the op-amp gives an accuracy of 60µV at 40MHz.

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What this paper is about

This paper presents the design and implementation of a high-speed, high-gain fully differential opamp. The architecture consists of a telescopic cascode differential amplifier followed by a modified common-source second stage that includes an intermediate push-pull stage, individual CMFB circuits including frequency compensation for the first and second stages, RC Miller compensation for the main op-amp, and dc bias circuit blocks. The circuit is implemented in SCL 180nm technology, including layout and post-layout extracted characterization. It achieves a DC gain of 90dB with phase margin of 58° at 530MHz for a load of 1pF. Output voltage swing is +/-600mV for a +/-900mV supply. A sample-and-hold circuit built with the op-amp gives an accuracy of 60µV at 40MHz.

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Available abstract

This paper presents the design and implementation of a high-speed, high-gain fully differential opamp. The architecture consists of a telescopic cascode differential amplifier followed by a modified common-source second stage that includes an intermediate push-pull stage, individual CMFB circuits including frequency compensation for the first and second stages, RC Miller compensation for the main op-amp, and dc bias circuit blocks. The circuit is implemented in SCL 180nm technology, including layout and post-layout extracted characterization. It achieves a DC gain of 90dB with phase margin of 58° at 530MHz for a load of 1pF. Output voltage swing is +/-600mV for a +/-900mV supply. A sample-and-hold circuit built with the op-amp gives an accuracy of 60µV at 40MHz.

Key concepts: Operational amplifier, Phase margin, Computer science, Cascode, Compensation (psychology), Differential amplifier, Operational transconductance amplifier, Electronic engineering

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