Implementation research on digital decimation filter in ground motion observation system

In order to improve the integration level,reliability and reduce the total cost of a 6 degree-freedom strong ground motion observation system,its FIR decimation filter chip CS5322 of ∑-Δ type A/D converter chip set in the system are replaced by FPGA.According to the character of FPGA,the FIR digital decimation filter is implemented via using distribution algorithms which are based on the technique of looking up table.In the same time,the usage of the FPGA embedded resources is reduced greatly because of using partial LUT configuration to implement the distribution algorithms.3 FIR decimation filters in CS5322 are designed respectively by using this method.Equivalent functions of 8 CS5322 chips are integrated into only one low cost EP1C12 chip,and the design target is achieved.