FPGA Implementation of Square Root Raised Cosine Pulse Shaping Filter

The FPGA implementation of look-up table arithmetic-based square root raised cosine pulse shaping filter in communication system based on circuit segmentation is proposed,and how to calculate the initialization ROM data of a forming waveform is discussed.On this basis,the VHDL code and the Modelsim simulation results are elucidated.The design method is simple and easy,and is very suitable for high speed forming application.