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2006•Journal of Heilongjiang Hydraulic Engineering CollegeRequires access

Design of MBA-WT Multiplier Based on VHDL

Fan Tie-qiang

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Abstract

In this paper,the algorithm of high speed multiplier is analyzed and a 16-bit MBA-WT multiplier is proposed based on VHDL language.The multiplier is provided employed modified Booth algorithm(MBA) and Wallace Tree to reduce the number of partial product and to save the time cost for adding reduce to O(logN),finally CLA is used to get the result at higher speed.The whole design is complemented by VHDL and simulated by Modelsim Synplify.

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In this paper,the algorithm of high speed multiplier is analyzed and a 16-bit MBA-WT multiplier is proposed based on VHDL language.The multiplier is provided employed modified Booth algorithm(MBA) and Wallace Tree to reduce the number of partial product and to save the time cost for adding reduce to O(logN),finally CLA is used to get the result at higher speed.The whole design is complemented by VHDL and simulated by Modelsim Synplify.

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Available abstract

In this paper,the algorithm of high speed multiplier is analyzed and a 16-bit MBA-WT multiplier is proposed based on VHDL language.The multiplier is provided employed modified Booth algorithm(MBA) and Wallace Tree to reduce the number of partial product and to save the time cost for adding reduce to O(logN),finally CLA is used to get the result at higher speed.The whole design is complemented by VHDL and simulated by Modelsim Synplify.

Key concepts: ModelSim, VHDL, Multiplier (economics), Computer science, Arithmetic, Field-programmable gate array, Algorithm, Mathematics

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