Design and Implementation of LDPC Decoder for DVB-S2

The hardware architecture of the DVB-S2 LDPC(Low Density Parity Check Code) code decoder is researched.According to the cyclical feature of the check matrix we have realized a decoder of the DVB-S2 LDPC code whose rate is 3/5 and length is 16 200 bit.Experiment result shows that the total consumption of the LDPC decoder are 24 004 logic cells,6 437 registers and 448 594 bits of RAM.And the throughput of is up to 289 Mbit/s.The structure of decoder using shared memory banks and writing the LLR(Log-Likelihood Ratio) back to the RAM has low area and high throughput.