A Low Power Embedded 14-bit 400 MHz DAC

A low power embedded 14-bit 400 MHz digital-to-analog converter(DAC) for high speed frequency synthesizer application is presented. The 5+4+5 segmented current-steering architecture is employed in the DAC. The output stage of return-to-zero scheme is used to enhance the dynamic performance of spurious-free dynamic range (SFDR). The DAC core is fabricated in a 1P6M 0.18 μm Mixed signal CMOS technology and occupies a die area of only 1.1 mm×0.87 mm. The measured differential nonlinearity lies between-0.9 LSB and+0.5 LSB,the measured integral nonlinearity lies between-1.4 LSB and+1.3 LSB. The measured SFDR for a 80 MHz output signal at 400 MHz sampling clock rate is 76.47 dB,the power consumption is only 107.2 mW.