Design and FPGA Implementation of Reed-Solomon Coder / Decoder Based on IP Core

The RS( Reed-Solomon) IP Core from Altera Company is of great functions,but to use the IP Core,the design of the correlative alternation signal is necessary. The paper introduces a method of RS Coder / Decoder design based on the IP Core. The timing principle of the RS IP Core alternation signal is analyzed,and the corresponding signal-producing module of RS Coder / Decoder is designed. The method of parameter configuring and usage of the RS IP Core is also introduced,and the top – module diagram is provided. To validate the correctness of the design,the Coder / Decoder is simulated. To test the limit of its error-correcting performance,a continuous stream of coded symbols,which has the maximum error symbols,is simulated and tested. The test results of the timing simulation indicate that the RS decoder has the maximum error-correcting performance.