ScholarLens Back to search
2004•Unpublished venueRequires access

Design and Implementation of a Parallel Priority Interrupt System in Fast MCU's

Feng Ran

Open publisher page 0 citations

Abstract

Traditional Micro-Controller Unit (MCU) usually uses daisy chain interrupt hardware. It is much a waste of time that MCU polls interrupt sources according to their orders of priority each time. Based on a multi-level interrupt system with two priorities and eleven maskable interrupts, a parallel priority interrupt hardware, illustrated with program flow chart, is proposed. Embedded in a fast 8051 compatible MCU core, the interrupt system is verified by stretching port pins of MCU core from FPGA development board of Altera APEX20KE into various microcontroller application systems.

About this research paper

What this paper is about

Traditional Micro-Controller Unit (MCU) usually uses daisy chain interrupt hardware. It is much a waste of time that MCU polls interrupt sources according to their orders of priority each time. Based on a multi-level interrupt system with two priorities and eleven maskable interrupts, a parallel priority interrupt hardware, illustrated with program flow chart, is proposed. Embedded in a fast 8051 compatible MCU core, the interrupt system is verified by stretching port pins of MCU core from FPGA development board of Altera APEX20KE into various microcontroller application systems.

Why it matters

A significance statement is not available in the OpenAlex record.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

Traditional Micro-Controller Unit (MCU) usually uses daisy chain interrupt hardware. It is much a waste of time that MCU polls interrupt sources according to their orders of priority each time. Based on a multi-level interrupt system with two priorities and eleven maskable interrupts, a parallel priority interrupt hardware, illustrated with program flow chart, is proposed. Embedded in a fast 8051 compatible MCU core, the interrupt system is verified by stretching port pins of MCU core from FPGA development board of Altera APEX20KE into various microcontroller application systems.

Key concepts: Interrupt, Microcontroller, Embedded system, Interrupt handler, Computer science, Computer hardware, Field-programmable gate array, Flow chart

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
Design and Implementation of a Parallel Priority Interrupt System in Fast MCU's — Research Paper | ScholarLens