2005Computer Engineering and ScienceRequires access

A Group-Based Timing-Driven Floorplan Method

Sikun Li

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Abstract

This paper proposes a timing-driven floorplan method based on groups in the physical design. This method employs available EDA tools and partitions the netlist into groups, and then utilizes the architecture experience of designers to layout, adjust and optimize the netlist. This method can backannotate the better custom wire load model to the synthesis and improve the consistency between the synthesis and layout. This method can also distribute the power and ground network based on groups and make it easy to route successfully. The experimental results on a 32 bits microprocessor, which has been tapouted successfully, show that the method can improve the timing of critical paths and accelerate the process of physical design.

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What this paper is about

This paper proposes a timing-driven floorplan method based on groups in the physical design. This method employs available EDA tools and partitions the netlist into groups, and then utilizes the architecture experience of designers to layout, adjust and optimize the netlist. This method can backannotate the better custom wire load model to the synthesis and improve the consistency between the synthesis and layout. This method can also distribute the power and ground network based on groups and make it easy to route successfully. The experimental results on a 32 bits microprocessor, which has been tapouted successfully, show that the method can improve the timing of critical paths and accelerate the process of physical design.

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Available abstract

This paper proposes a timing-driven floorplan method based on groups in the physical design. This method employs available EDA tools and partitions the netlist into groups, and then utilizes the architecture experience of designers to layout, adjust and optimize the netlist. This method can backannotate the better custom wire load model to the synthesis and improve the consistency between the synthesis and layout. This method can also distribute the power and ground network based on groups and make it easy to route successfully. The experimental results on a 32 bits microprocessor, which has been tapouted successfully, show that the method can improve the timing of critical paths and accelerate the process of physical design.

Key concepts: Netlist, Floorplan, Computer science, Physical design, Static timing analysis, Microprocessor, Process (computing), Embedded system

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